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pulley: Implement iadd_pairwise #9912

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merged 4 commits into from
Dec 30, 2024
Merged

pulley: Implement iadd_pairwise #9912

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6fe66a9
pulley: Implement iadd_pairwise
eagr Dec 29, 2024
77b3b09
access by index
eagr Dec 30, 2024
89a3af5
Merge branch 'main' into pulley-pairwise
eagr Dec 30, 2024
f15d167
Merge branch 'main' into pulley-pairwise
eagr Dec 30, 2024
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7 changes: 6 additions & 1 deletion cranelift/codegen/src/isa/pulley_shared/lower.isle
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Original file line number Diff line number Diff line change
Expand Up @@ -221,6 +221,11 @@
(rule 1 (lower (has_type $I32X4 (iadd a b))) (pulley_vaddi32x4 a b))
(rule 1 (lower (has_type $I64X2 (iadd a b))) (pulley_vaddi64x2 a b))

;;;; Rules for `iadd_pairwise` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

(rule (lower (has_type $I16X8 (iadd_pairwise a b))) (pulley_vaddpairwisei16x8_s a b))
(rule (lower (has_type $I32X4 (iadd_pairwise a b))) (pulley_vaddpairwisei32x4_s a b))

;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

(rule 0 (lower (has_type (ty_int (fits_in_32 _)) (isub a b))) (pulley_xsub32 a b))
Expand Down Expand Up @@ -1372,4 +1377,4 @@

;;;; Rules for `swizzle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

(rule 1 (lower (has_type $I8X16 (swizzle a b))) (pulley_vswizzlei8x16 a b))
(rule 1 (lower (has_type $I8X16 (swizzle a b))) (pulley_vswizzlei8x16 a b))
5 changes: 0 additions & 5 deletions crates/wast-util/src/lib.rs
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Expand Up @@ -407,11 +407,9 @@ impl WastTest {
"spec_testsuite/proposals/annotations/simd_lane.wast",
"spec_testsuite/proposals/relaxed-simd/i16x8_relaxed_q15mulr_s.wast",
"spec_testsuite/proposals/relaxed-simd/i32x4_relaxed_trunc.wast",
"spec_testsuite/proposals/relaxed-simd/relaxed_dot_product.wast",
"spec_testsuite/proposals/relaxed-simd/relaxed_madd_nmadd.wast",
"spec_testsuite/proposals/memory64/simd_lane.wast",
"spec_testsuite/proposals/memory64/relaxed_madd_nmadd.wast",
"spec_testsuite/proposals/memory64/relaxed_dot_product.wast",
"spec_testsuite/proposals/memory64/i16x8_relaxed_q15mulr_s.wast",
"spec_testsuite/proposals/memory64/i32x4_relaxed_trunc.wast",
"spec_testsuite/simd_f32x4_arith.wast",
Expand All @@ -420,12 +418,9 @@ impl WastTest {
"spec_testsuite/simd_f64x2_arith.wast",
"spec_testsuite/simd_f64x2_cmp.wast",
"spec_testsuite/simd_f64x2_pmin_pmax.wast",
"spec_testsuite/simd_i16x8_extadd_pairwise_i8x16.wast",
"spec_testsuite/simd_i16x8_q15mulr_sat_s.wast",
"spec_testsuite/simd_i16x8_sat_arith.wast",
"spec_testsuite/simd_i32x4_arith2.wast",
"spec_testsuite/simd_i32x4_dot_i16x8.wast",
"spec_testsuite/simd_i32x4_extadd_pairwise_i16x8.wast",
"spec_testsuite/simd_i32x4_trunc_sat_f32x4.wast",
"spec_testsuite/simd_i32x4_trunc_sat_f64x2.wast",
"spec_testsuite/simd_i64x2_arith2.wast",
Expand Down
34 changes: 34 additions & 0 deletions pulley/src/interp.rs
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Expand Up @@ -3299,6 +3299,40 @@ impl ExtendedOpVisitor for Interpreter<'_> {
ControlFlow::Continue(())
}

fn vaddpairwisei16x8_s(&mut self, operands: BinaryOperands<VReg>) -> ControlFlow<Done> {
let a = self.state[operands.src1].get_i16x8();
let b = self.state[operands.src2].get_i16x8();
let result = a
.chunks(2)
.chain(b.chunks(2))
.map(|pair| {
let [h, t]: [_; 2] = pair.try_into().unwrap();
h.wrapping_add(t)
})
.collect::<Vec<_>>()
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For these instructions we'll definitely want to avoid an intermediate allocation of a Vec. It might be reasonable to just use manual indices here and/or "macro expanding" some code. I don't think the standard library helpers for all this are necessarily the best way to go.

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@Xuanwo Xuanwo Dec 30, 2024 •
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We only have limited numbers of items to operate, maybe we can just write them out like:

fn vaddpairwisei16x8_s(&mut self, operands: BinaryOperands<VReg>) -> ControlFlow<Done> {
    let a = self.state[operands.src1].get_i16x8();
    let b = self.state[operands.src2].get_i16x8();
    
    let mut result = [0i16; 8];
    
    // Process first 4 elements from a
    result[0] = a[0].wrapping_add(a[1]);
    result[1] = a[2].wrapping_add(a[3]);
    result[2] = a[4].wrapping_add(a[5]);
    result[3] = a[6].wrapping_add(a[7]);
    
    // Process first 4 elements from b 
    result[4] = b[0].wrapping_add(b[1]);
    result[5] = b[2].wrapping_add(b[3]);
    result[6] = b[4].wrapping_add(b[5]);
    result[7] = b[6].wrapping_add(b[7]);

    self.state[operands.dst].set_i16x8(result);
    ControlFlow::Continue(())
}

This also has a compiler to perform better analysis, I suppose.

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Guess I need a mind shift for this :)

.try_into()
.unwrap();
self.state[operands.dst].set_i16x8(result);
ControlFlow::Continue(())
}

fn vaddpairwisei32x4_s(&mut self, operands: BinaryOperands<VReg>) -> ControlFlow<Done> {
let a = self.state[operands.src1].get_i32x4();
let b = self.state[operands.src2].get_i32x4();
let result = a
.chunks(2)
.chain(b.chunks(2))
.map(|pair| {
let [h, t]: [_; 2] = pair.try_into().unwrap();
h.wrapping_add(t)
})
.collect::<Vec<_>>()
.try_into()
.unwrap();
self.state[operands.dst].set_i32x4(result);
ControlFlow::Continue(())
}

fn vshli8x16(&mut self, operands: BinaryOperands<VReg, VReg, XReg>) -> ControlFlow<Done> {
let a = self.state[operands.src1].get_i8x16();
let b = self.state[operands.src2].get_u32();
Expand Down
5 changes: 5 additions & 0 deletions pulley/src/lib.rs
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Expand Up @@ -899,6 +899,11 @@ macro_rules! for_each_extended_op {
/// `dst = src1 + src2`
vaddf64x2 = VAddF64x2 { operands: BinaryOperands<VReg> };

/// `dst = [src1[0] + src1[1], ..., src2[6] + src2[7]]`
vaddpairwisei16x8_s = VAddpairwiseI16x8S { operands: BinaryOperands<VReg> };
/// `dst = [src1[0] + src1[1], ..., src2[2] + src2[3]]`
vaddpairwisei32x4_s = VAddpairwiseI32x4S { operands: BinaryOperands<VReg> };

/// `dst = src1 << src2`
vshli8x16 = VShlI8x16 { operands: BinaryOperands<VReg, VReg, XReg> };
/// `dst = src1 << src2`
Expand Down
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